Embedded parallel divide-and-conquer video decompression algorithm and architecture for HDTV applications

DCT/IDCT based source coding and decoding techniques are widely accepted in HDTV systems and other MPEG based applications. We propose a new direct 2-D IDCT algorithm based on the parallel divide-and-conquer approach. The algorithm distributes computation by considering one transformed coefficient at a time and doing partial computation and updating as every coefficient arrives. A novel parallel and fully pipelined architecture with an effective processing time of one cycle per pixel for an N×N size block is designed to implement the algorithm. An unique feature of the architecture is that it integrates inverse-shuffling, inverse-quantization, inverse-source-coding and motion-compensation into a single compact data-path. The entire block of pixel values are sampled in a single cycle for post processing after decompression. We use only (N/2(N/2+1))/2 multipliers and N² adders. The configuration of the adders is such that motion compensation is realized in a single cycle following decompression