Modeling of VLSI RC parasitics based on the network reduction algorithm

Author

Niewczas, Mariusz ; Wojtasik, Adam

Author_Institution

Inst. of Microelectron. & Optoelectron., Warsaw Univ. of Technol., Poland

Volume

14

Issue

2

fYear

1995

fDate

2/1/1995 12:00:00 AM

Firstpage

137

Lastpage

144

Abstract

This paper presents a method of modeling of R and C parasitics in VLSI circuits. A network representation is generated for finite difference discretization of 2-D Laplace´s equation, and a reduction algorithm is applied to this network. The solution area can be defined by any set of polygons. If n is the number of discretization nodes the new algorithm is O(n^1.5). It yields directly the coefficients of capacitance or admittance matrix. In contrast to other methods, in the network reduction approach, the time required for modeling depends mainly upon the complexity of the solution area but weakly upon the number of terminals. This feature is particularly valuable in application to circuit extraction

Keywords

Laplace equations; VLSI; circuit analysis computing; computational complexity; digital simulation; equivalent circuits; finite difference methods; integrated circuit modelling; 2D Laplace´s equation; RC parasitics; VLSI; admittance matrix; capacitance matrix; circuit extraction; discretization nodes; finite difference discretization; network reduction algorithm; network representation; polygons; reduction algorithm; solution area; Admittance; Circuits; Computational complexity; Difference equations; Finite difference methods; Integral equations; Laplace equations; Parasitic capacitance; Sparse matrices; Very large scale integration;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.370431

Filename

370431