• DocumentCode
    749593
  • Title

    A high-level simulation and synthesis environment for ΔΣ modulators

  • Author

    Francken, Kenneth ; Gielen, Georges G E

  • Author_Institution
    Dept. of Electr. Eng., Katholieke Universiteit Leuven, Leuven-Heverlee, Belgium
  • Volume
    22
  • Issue
    8
  • fYear
    2003
  • Firstpage
    1049
  • Lastpage
    1061
  • Abstract
    An approach is presented for the high-level simulation and synthesis of discrete-time ΔΣ modulators based on a simulation-based optimization strategy. The high-level synthesis approach determines both the optimum modulator topology and the required building block specifications, such that the system specifications-mainly accuracy (dynamic range) and signal bandwidth-are satisfied at the lowest possible power consumption. A genetic-based differential evolution algorithm is used in combination with a fast dedicated behavioral simulator to realistically analyze and optimize the modulator performance. The approach has been implemented in a tool called Daisy (Delta-Sigma Analysis and Synthesis). Experimental results are shown for both the analysis and synthesis capabilities, illustrating the effectiveness of the approach. The selected range of optimized ΔΣ modulator topologies as a function of the modulator specifications for a wide range of values indicate the capabilities of and the performance range covered by the tool.
  • Keywords
    circuit CAD; circuit optimisation; circuit simulation; delta-sigma modulation; discrete time systems; genetic algorithms; high level synthesis; integrated circuit design; modulators; Daisy tool; building block specifications; discrete-time ΔΣ modulators; fast dedicated behavioral simulator; genetic algorithm; genetic-based differential evolution algorithm; high-level simulation environment; high-level synthesis environment; optimum modulator topology; simulation-based optimization strategy; Algorithm design and analysis; Analytical models; Delta modulation; Dynamic range; Energy consumption; Genetic algorithms; High level synthesis; Performance analysis; Signal synthesis; Topology;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2003.814954
  • Filename
    1214863