• DocumentCode
    751012
  • Title

    Improved lifetime of poly-Si TFTs with a self-aligned gate-overlapped LDD structure

  • Author

    Mishima, Yasuyoshi ; Ebiko, Yoshiki

  • Author_Institution
    Fujitsu Labs. Ltd., Atsugi, Japan
  • Volume
    49
  • Issue
    6
  • fYear
    2002
  • fDate
    6/1/2002 12:00:00 AM
  • Firstpage
    981
  • Lastpage
    985
  • Abstract
    We investigated the lifetimes for various poly-Si thin film transistor (TFT) structures. A gate-overlapped lightly doped drain (GOLDD) structure was self-aligned by the side etching of Al-Nd in an Al-Nd/Mo gate electrode. The dopant activation process in the LDD regions of GOLDD TFTs was performed by using a H2 ion-doping technique. We also observed the effect of lifetime on the source/drain activation process. The thermal annealing of the source/drain region was found to extend the lifetime. The predicted lifetime of our GOLDD poly-Si TFT is superior to those of non-lightly doped drain (non-LDD) and lightly-doped drain (LDD) poly-Si TFTs. The trapped-electron density at the drain junction after bias-stressing was also investigated using a two-dimensional (2-D) simulation
  • Keywords
    annealing; electron density; elemental semiconductors; etching; semiconductor device reliability; semiconductor doping; silicon; thin film transistors; Al-NdMo-SiO2-Si; dopant activation process; drain junction; ion-doping technique; polysilicon TFTs; self-aligned gate-overlapped LDD structure; side etching; thermal annealing; trapped-electron density; two-dimensional simulation; Annealing; Circuit simulation; Degradation; Doping; Electrodes; Etching; Fabrication; Plasma temperature; Thin film transistors; Two dimensional displays;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2002.1003716
  • Filename
    1003716