Capacitance Hysteresis in the High-k/Metal Gate-Stack From Pulsed Measurement

An unusual hysteresis is observed while measuring the capacitance-voltage (C-V) curve of the high-k/metal gate-stack using a pulsed-voltage technique. The hysteresis is found to vary only with the voltage ramp rate but not with the voltage pulse width. The C-V curve derived from the negative-to-positive (forward) voltage ramp has a consistently more positive flat ba5412279nd voltage than that obtained by the positive-to-negative (reverse) voltage ramp. The relative positions of the forward and reverse C-V curves are opposite to those measured using the quasi-static voltage-sweep method. Charge trapping/detrapping in the high-k oxide could not consistently account for these observations. An alternative explanation based on the lag in interface dipole response is proposed.