• DocumentCode
    75188
  • Title

    Adaptive Multiset Stochastic Decoding of Non-Binary LDPC Codes

  • Author

    Ciobanu, Amelia ; Hemati, Saied ; Gross, Warren J.

  • Author_Institution
    Dept. of the Electr. & Comput. Eng., McGill Univ., Montreal, QC, Canada
  • Volume
    61
  • Issue
    16
  • fYear
    2013
  • fDate
    Aug.15, 2013
  • Firstpage
    4100
  • Lastpage
    4113
  • Abstract
    We propose a non-binary stochastic decoding algorithm for low-density parity-check (LDPC) codes over GF(q) with degree two variable nodes, called Adaptive Multiset Stochastic Algorithm (AMSA). The algorithm uses multisets, an extension of sets that allows multiple occurrences of an element, to represent probability mass functions that simplifies the structure of the variable nodes. The run-time complexity of one decoding cycle using AMSA is O(q) for conventional memory architectures, and O(1) if a custom memory architecture is used. Two fully-parallel AMSA decoders are implemented on FPGA for two (192,96) (2,4)-regular codes over GF(64) and GF(256), both achieving a maximum clock frequency of 108 MHz. The GF(64) decoder has a coded throughput of 65 Mb/s at Eb/N0=2.4 dB when using conventional memory, while a decoder using the custom memory version can achieve 698 Mb/s at the same Eb/N0. At a frame error rate (FER) of 2×10-6 the GF(64) version of the algorithm is only 0.04 dB away from the floating-point SPA performance, and for the GF(256) code the difference is 0.2 dB. To the best of our knowledge, this is the first fully parallel non-binary LDPC decoder over GF(256) reported in the literature.
  • Keywords
    adaptive decoding; codecs; parity check codes; stochastic processes; AMSA decoders; FPGA implementation; adaptive multiset stochastic algorithm; adaptive multiset stochastic decoding; bit rate 65 Mbit/s; bit rate 698 Mbit/s; frequency 108 MHz; low-density parity-check codes; memory architectures; nonbinary LDPC codes; probability mass functions; run-time complexity; Iterative decoding; low-density parity-check code; non-binary codes; parallel architectures; stochastic decoding;
  • fLanguage
    English
  • Journal_Title
    Signal Processing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1053-587X
  • Type

    jour

  • DOI
    10.1109/TSP.2013.2264813
  • Filename
    6519310