CMOS VLSI single event transient characterization

Author

Heileman, Steven J. ; Eisenstadt, William R. ; Fox, Robert M. ; Wagner, Ronald S. ; Bordes, Nicole ; Bradley, Jeffrey M.

Author_Institution

Florida Univ., Gainesville, FL, USA

Volume

36

Issue

6

fYear

1989

fDate

12/1/1989 12:00:00 AM

Firstpage

2287

Lastpage

2291

Abstract

The MOSIS VLSI IC process has been characterized for picosecond single-event transients for large-area diode test structures. Three test structures were designed for a CMOS, p-well, 3-μm process, including two MOS diodes for SEU transient measurements. Devices were irradiated with 5-MeV boron ions and 5-MeV α-particles. Bulk CMOS single-event transients are found to exhibit a wide variety of electrical interactions when the devices are irradiated, owing to complex technology profiles and multijunction effects. The transients characterized in this work can be used to simulate single-event upsets in SRAM (static RAM) circuits

Keywords

CMOS integrated circuits; VLSI; alpha-particle effects; environmental testing; integrated circuit testing; integrated memory circuits; ion beam effects; radiation hardening (electronics); random-access storage; 3 micron; 5 MeV; B ions; Bulk CMOS; CMOS VLSI single event transient characterization; MOS diodes; MOSIS VLSI IC process; SEU; SEU transient measurements; SRAM; alpha particles; electrical interactions; large-area diode test structures; multijunction effects; picosecond single-event transients; single-event upsets; Atherosclerosis; Bonding; CMOS process; Circuit testing; Computer simulation; Diodes; Laboratories; Random access memory; Single event upset; Very large scale integration;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.45437

Filename

45437