DocumentCode
753593
Title
LSI Processor for Digital Signal Processing and Its Application to 4800 Bit/s Modem
Author
Murano, Kazuo ; Unagami, Shigeyuki ; Tsuda, Toshitaka
Author_Institution
Fujitsu Lab. Ltd.,Japan
Volume
26
Issue
5
fYear
1978
fDate
5/1/1978 12:00:00 AM
Firstpage
499
Lastpage
506
Abstract
This paper describes a fast data processing LSI unit tailored to the digital signal processing (DSP) applications in the field of electrical communications. The results of successful application to the 4800 bit/s modem are also given. The LSI processor discussed here adopts a firmware control scheme to enhance the flexibility and freedom of application and extensively utilizes the pipeline processing technique to attain high speed data handling capability. The various operations encountered in DSP systems are unified into one operation of the type
and the LSI processor is designed to continuously perform this operation, while the data to be operated are transferred sequentially into the processor controlled by exterior firmware. The developed LSI handles 8 bit data at the clock frequency of 1.152 MHz and manages 144 K operations per second (6.9 μs cycle time). The LSI is an N-MOS chip containing 1500 gates and packaged in a 40 pin DIP. The automatic equalizer for 4800 bit/s modem was implemented using two of the developed LSI processors and about 4 K ROM and 1 K RAM memory chips. The measurement on this modem gave the error rate of 10-5at
dB and error free phase jitter allowance of 55° p-p. Application of the LSI processor to digital filters for roll-off spectrum shaping and timing signal extraction is also described.
and the LSI processor is designed to continuously perform this operation, while the data to be operated are transferred sequentially into the processor controlled by exterior firmware. The developed LSI handles 8 bit data at the clock frequency of 1.152 MHz and manages 144 K operations per second (6.9 μs cycle time). The LSI is an N-MOS chip containing 1500 gates and packaged in a 40 pin DIP. The automatic equalizer for 4800 bit/s modem was implemented using two of the developed LSI processors and about 4 K ROM and 1 K RAM memory chips. The measurement on this modem gave the error rate of 10-5at
dB and error free phase jitter allowance of 55° p-p. Application of the LSI processor to digital filters for roll-off spectrum shaping and timing signal extraction is also described.Keywords
Adaptive equalizers; Computer pipeline processing; Digital modulation/demodulation; MOSFET digital integrated circuits; PSK modulation/demodulation; Signal processing; Automatic control; Communication system control; Data handling; Data processing; Digital signal processing; Large scale integration; Microprogramming; Modems; Pipeline processing; Process design;
fLanguage
English
Journal_Title
Communications, IEEE Transactions on
Publisher
ieee
ISSN
0090-6778
Type
jour
DOI
10.1109/TCOM.1978.1094105
Filename
1094105
Link To Document