Leakage sources and possible solutions in nanometer CMOS technologies

Until recent years, dynamic power dissipation contributed the most to the chip´s total power dissipation in CMOS digital circuits thus much attention was given to reduce this dynamic power. But as technology advances into the sub-100 nm regime, leakage power dissipation, which is a static power, increases at a much faster rate than dynamic power and it is expected to dominate the chips´ total power dissipation. According to the 2004 update of the International Technology Roadmap for Semiconductors (ITRS), the required reduction of dynamic power beyond the reduction already given by technology scaling for a System-On-Chip (SOC) will grow from 0.1 in 2005 up to 8.1 reduction in 2018; at the same time the required reduction of a SOC standby power will exponentially grow from 2.4 in 2005 up to 232 in 20181.