DocumentCode
755387
Title
Settling time analysis of a replica-amp gain enhanced operational amplifier
Author
Yu, Paul C. ; Lee, Hae-Seung
Author_Institution
Microsystems Technol. Lab., MIT, Cambridge, MA, USA
Volume
42
Issue
3
fYear
1995
fDate
3/1/1995 12:00:00 AM
Firstpage
137
Lastpage
142
Abstract
The effect of a replica-amp gain enhancement technique on the settling time of a two-stage op-amp is analyzed. It is found that since the added poles and zeros are comparable to the closed-loop bandwidth, there is only a small effect on the settling time. This analytical result is confirmed by both SPICE simulation and test-chip measurements
Keywords
SPICE; circuit analysis computing; equivalent circuits; linear network analysis; operational amplifiers; poles and zeros; SPICE simulation; closed-loop bandwidth; gain enhancement technique; operational amplifier; poles and zeros; replica-amp gain enhanced opamp; settling time analysis; two-stage op-amp; Analytical models; Bandwidth; Circuit simulation; Circuit testing; Electrical resistance measurement; Feedback; Operational amplifiers; Poles and zeros; SPICE; Voltage;
fLanguage
English
Journal_Title
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
Publisher
ieee
ISSN
1057-7130
Type
jour
DOI
10.1109/82.372863
Filename
372863
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