An architecture and an algorithm for fully digital correction of monolithic pipelined ADCs

Accurate trimming of the analog circuitry in analog/digital converters beyond 12 b is difficult. An alternative approach allows a margin of errors on all analog components and compensates for it in the digital domain. This paper describes such a method for pipelined or cyclic converters. Unlike in sigma-delta converters, no over-sampling is required. A powerful identification algorithm determines a limited number of digital coefficients, that linearize the response. No external measurement hardware is needed. Based on the known performance of state-of-the-art analog blocks, linearity of 16 b at multi-MHz sampling rates seems achievable