• DocumentCode
    755975
  • Title

    Extracting solid conductors from a single triangulated surface representation for interconnect analysis

  • Author

    Sefler, John F. ; Neureuther, Andrew R.

  • Author_Institution
    Comput. Sci. Div., California Univ., Berkeley, CA, USA
  • Volume
    9
  • Issue
    1
  • fYear
    1996
  • fDate
    2/1/1996 12:00:00 AM
  • Firstpage
    82
  • Lastpage
    86
  • Abstract
    A method has been developed for extracting solid geometry from a single surface and has been used to link three-dimensional topography simulation with three-dimensional interconnect analysis. It begins with the intersection of multiple triangulated surfaces to enclose the desired solid, followed by the removal of unwanted surfaces using the deloop algorithm and a new algorithm for the removal of thin triangles. The thin triangle removal algorithm runs in O(n) time and can remove a large number of unnecessary facets without significantly altering the surface topography. The solid extraction algorithm runs in O(n·lg n) time, limited by the performance of the deloop algorithm. The solid extraction capability enables more accurate three-dimensional interconnect analyses to be performed on rigorously simulated topography using tools such as FASTCAP from M.I.T. For comparison, FASTCAP analyses have been performed on polysilicon elbows generated by simple mask extrusion and a more rigorous SAMPLE-3D simulation. Results show differences up to 44% in capacitance values between the mask extrusion model and SAMPLE-3D topography
  • Keywords
    computational geometry; integrated circuit interconnections; semiconductor process modelling; solid modelling; surface topography; FASTCAP; SAMPLE-3D simulation; capacitance values; deloop algorithm; interconnect analysis; mask extrusion; multiple triangulated surfaces; polysilicon elbows; single triangulated surface representation; solid conductor extraction; solid extraction algorithm; solid geometry; thin triangle removal; three-dimensional interconnect analyses; three-dimensional topography simulation; Analytical models; Circuit simulation; Conductors; Elbow; Etching; Integrated circuit interconnections; Lithography; Resists; Solid modeling; Surface topography;
  • fLanguage
    English
  • Journal_Title
    Semiconductor Manufacturing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0894-6507
  • Type

    jour

  • DOI
    10.1109/66.484286
  • Filename
    484286