DocumentCode
756018
Title
The effect of silicon gate microstructure and gate oxide process on threshold voltage instabilities in p+-gate p-channel MOSFETs with fluorine incorporation
Author
Tseng, Hsing-Huang ; Tobin, Philip J. ; Baker, Frank K. ; Pfiester, James R. ; Evans, Keenan ; Fejes, Peter L.
Author_Institution
Motorola Inc., Austin, TX, USA
Volume
39
Issue
7
fYear
1992
fDate
7/1/1992 12:00:00 AM
Firstpage
1687
Lastpage
1693
Abstract
Several phenomena have been identified which significantly reduce boron penetration for boron difluoride-implanted or boron/fluorine-co-implanted gates The fluorine-induced threshold-voltage (V TP) shift is minimized by using an as-deposited amorphous silicon gate and a gate oxide process that excludes hydrogen chloride. The V TP shift can be reduced to a level close to that of a boron-implanted gate, while maintaining the fluorine incorporation at the SiO2/Si interface to lower interface-state density. A model based on the fluorine atom distribution is proposed to explain the observed V TP shift
Keywords
insulated gate field effect transistors; interface electron states; ion implantation; semiconductor technology; Si-SiO2; fluorine incorporation; gate microstructure; gate oxide process; p+-gate p-channel MOSFETs; threshold voltage instabilities; Amorphous silicon; Annealing; Boron; Capacitors; Fabrication; Hydrogen; Implants; MOS devices; Microstructure; Threshold voltage;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.141235
Filename
141235
Link To Document