Reduced trapping effects and improved electrical performance in buried-gate 4H-SiC MESFETs

Surface effects on the current instability of 4H-SiC MESFETs were studied by comparing different surface structures. The current instability phenomenon was illustrated by bias sweeping methods and current recovery time measurements. A reduction in the current instability was observed for gate-recessed and buried-gate devices compared to the nonrecessed and channel-recessed devices. In addition, the buried-gate devices were found to have higher current density and breakdown voltage compared to the gate-recessed devices, resulting from their shorter effective gate length and lower electric field distribution under the gate, respectively. With high saturation current, high breakdown voltage, and much reduced surface effects, the buried-gate structure is a candidate for high-power SiC MESFETs.