The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series

Author

Chang, Jonathan ; Huang, Ming ; Shoemaker, Jonathan ; Benoit, John ; Chen, Szu-Liang ; Chen, Wei ; Chiu, Siufu ; Ganesan, Raghuraman ; Leong, Gloria ; Lukka, Venkata ; Rusu, Stefan ; Srivastava, Durgesh

Author_Institution

Intel Corp., Santa Clara, CA

Volume

42

Issue

4

fYear

2007

fDate

4/1/2007 12:00:00 AM

Firstpage

846

Lastpage

852

Abstract

The 16-way set associative, single-ported 16-MB cache for the Dual-Core Intel Xeon Processor 7100 Series uses a 0.624 mum² cell in a 65-nm 8-metal technology. Low power techniques are implemented in the L3 cache to minimize both leakage and dynamic power. Sleep transistors are used in the SRAM array and peripherals, reducing the cache leakage by more than 2X. Only 0.8% of the cache is powered up for a cache access. Dynamic cache line disable (Intel Cache Safe Technology) with a history buffer protects the cache from latent defects and infant mortality failures

Keywords

cache storage; content-addressable storage; low-power electronics; microprocessor chips; 16 Mbit; 65 nm; 8-metal technology; Intel Cache Safe Technology; SRAM array; cache access; computer architecture; dual-core Intel Xeon processor 7100 Series; dynamic cache line disable; history buffer; infant mortality failures; latent defects; low power techniques; power reduction; reduced cache leakage; set associative cache; shared on-die L3 cache; sleep transistors; Computer aided manufacturing; Computer architecture; History; Logic arrays; Protection; Random access memory; Redundancy; Sleep; Testing; Voltage; Circuit design; computer architecture; manufacturability; microprocessor; on-die cache; power reduction; reliability; test;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2007.892185

Filename

4140574