A – $21.2$ -dBm Dual-Channel UHF Passive CMOS RFID Tag Design

Previous research results showed that UHF passive CMOS RFID tags had difficulty to achieve sensitivity less than -20 dBm. This paper presents a dual-channel 15-bit UHF passive CMOS RFID tag prototype that can work at sensitivity lower than -20 dBm. The proposed tag chip harvests energy and backscatters uplink data at 866.4-MHz (for ETSI) or 925-MHz (for FCC) channel and receives downlink data at 433-MHz channel. Consequently, the downlink data transmission does not interrupt our tag from harvesting RF energy. To use the harvested energy efficiently, we design a tag chip that includes neither a regulator nor a VCO such that the harvested energy is completely used in receiving, processing, and backscattering data. Without a regulator, our tag uses as few active analog circuits as possible in the receiver front-end. Instead, our tag uses a novel digital circuit to decode the received data. Without a VCO, the design of our tag can extract the required clock signal from the downlink data. Measurement result shows that the sensitivity of the proposed passive tag chip can reach down to -21.2 dBm. Such result corresponds to a 19.6-m reader-to-tag distance under 36-dBm EIRP and 0.4-dBi tag antenna gain. The chip was fabricated in TSMC 0.18- μm CMOS process. The die area is 0.958 mm ×0.931mm.