Numerical analysis of alpha-particle-induced soft errors in floating channel type surrounding gate transistor (FC-SGT) DRAM cell

This paper clarifies alpha-particle-induced soft error mechanisms in floating channel type surrounding gate transistor (FC-SGT) DRAM cells. One FC-SGT DRAM cell consists of an FC-SGT and a three-dimensional (3-D) storage capacitor. The cell itself arranges bit line (BL), storage node and body region in a silicon pillar vertically and achieves cell area of 4F² (F: feature size) per bit. In FC-SGT DRAM cells, the parasitic bipolar current is a major factor to cause soft errors. When an alpha particle penetrates the silicon pillar, generated electrons are collected to the storage node or BL due to the tunneling and diffusion mechanisms. On the other hand, holes are swept into the body region and accumulated. Consequently, the current flows not only in the surface but also in the entire body region due to the floating body effect. This parasitic bipolar current becomes the largest when an alpha particle penetrates the silicon pillar along the vertical axis. However, in case of FC-SGT DRAM cells, the surrounding gate structure can suppress the floating body effect compared with floating channel type SOI DRAM cells. As a result, the loss of the stored charge in the storage capacitor can be drastically decreased by using FC-SGT DRAM cell. Therefore, FC-SGT DRAM is a promising candidate for future high-density DRAMs having high soft-error immunity.