Design of an Integrated Circuit for the T1C Low-Power Line Repeater

A low-power T1C (3.152-Mbits/s) digital repeater has been designed which reduces the power requirements by a factor of approximately four compared to the previous version. The new design operates at 60 mA and 6.2 V, or 372 mW, a power level essentially identical to new T1 repeater designs which run at one-half the T1C rate. As a result, the maximum distance between powering stations has been increased from approximately 22 to 44 mi. The silicon integratedcircuit chip contains all the active circuitry necessary for one-way regeneration. The circuitry used for equalization, clock extraction, and regeneration are described in detail. Complementary bipolar (CBIC) technology, which made possible the power reduction and improved performance, is described in general terms.