DocumentCode
756897
Title
New nonvolatile memory with charge-trapping sidewall
Author
Fukuda, M. ; Nakanishi, T. ; Nara, Y.
Author_Institution
Fujitsu Labs. Ltd., Atsugi, Japan
Volume
24
Issue
7
fYear
2003
fDate
7/1/2003 12:00:00 AM
Firstpage
490
Lastpage
492
Abstract
This letter reports on the development of a new nonvolatile memory with charge-trapping sidewalls using sub-0.1-μm MOSFET technology. This memory has silicon nitride (SiN) sidewalls at both sides of the gate to store the charge. We have found that optimization of the p-n junction edge with the sidewall enables writing, reading, and erasing a 2-bit charge independently. The Vth window, which is the difference in the threshold voltage between forward and reverse read, was about 0.8 V with a gate length of 0.4 μm. In addition, it is scalable to 40 nm of the gate length. This device is attractive not only from the prospects of future size reduction, but also its compatibility with CMOS process.
Keywords
CMOS memory circuits; MOSFET; circuit simulation; integrated circuit modelling; 0.1 micron; 0.4 micron; 0.8 V; CMOS; MOSFET technology; SiN; charge-trapping sidewall; forward read; gate length; nonvolatile memory; p-n junction edge; reverse read; threshold voltage; Electrodes; MOSFET circuits; Medical simulation; Nonvolatile memory; P-n junctions; SONOS devices; Scalability; Semiconductor films; Silicon compounds; Writing;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/LED.2003.815002
Filename
1217307
Link To Document