DocumentCode
75803
Title
A Reconfigurable Platform and Programming Tools for High-Level Network Applications Demonstrated as a Hardware Honeypot
Author
Muhlbach, Sascha ; Koch, Andreas
Author_Institution
Center for Adv. Security Res. Darmstadt (CASED), Darmstadt, Germany
Volume
32
Issue
10
fYear
2014
fDate
Oct. 2014
Firstpage
1919
Lastpage
1932
Abstract
The security of computer systems and networks is severely threatened today by the combination of novel attack patterns and high traffic volumes. Together, this often exceeds the capabilities of purely software-based network security systems. As an alternative, hardware acceleration has been employed, e.g., for performing deep-packet inspection and pattern matching as well as general packet-header processing. While such implementations, capable of handling lower protocol layers, have been extensively studied in research and industry, their extension to higher communication layers has only rarely been addressed. Such capabilities, including the application level (OSI Layer 7), are the focus of this work. We present the NetStage platform, employing reconfigurable computing for high-throughput low-latency network processing, as well as associated development tools that allow networking domain experts to easily customize the system. As a use-case, we consider the realization of high-performance attack-resilient honeypots based on NetStage. To this end, we introduce the Malacoda language, its programming tools, and the generated target microarchitecture. We then evaluate the performance of Malacoda-generated vulnerability emulation handlers running on the NetStage platform.
Keywords
computer network security; field programmable gate arrays; Malacoda-generated vulnerability emulation handlers; NetStage platform; attack patterns; computer network security; computer system security; deep-packet inspection; hardware honeypot; high-level network applications; high-throughput low-latency network processing; packet-header processing; pattern matching; traffic volume; Field programmable gate arrays; Hardware; IP networks; Internet; Protocols; Routing; Security; 10G; FPGA; Network security; deep packet inspection; network stack;
fLanguage
English
Journal_Title
Selected Areas in Communications, IEEE Journal on
Publisher
ieee
ISSN
0733-8716
Type
jour
DOI
10.1109/JSAC.2014.2358838
Filename
6902760
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