DocumentCode
759241
Title
Optimization techniques for high order phase-locked loop type jitter reduction circuit for digital audio
Author
Wong, W.K.
Author_Institution
Dept. of Electron. Eng., City Univ. of Hong Kong, Hong Kong
Volume
42
Issue
1
fYear
1996
fDate
2/1/1996 12:00:00 AM
Firstpage
156
Lastpage
163
Abstract
Techniques like gain peaking reduction and the selection of voltage-controlled-crystal-oscillator´s (VCXO) frequency are addressed in this paper. The new gain peaking reduction criterion provides far better sampling jitter attenuation when compared with that using maximum phase margin
Keywords
Hi-Fi equipment; audio equipment; audio-frequency oscillators; circuit optimisation; crystal oscillators; jitter; phase locked loops; phase locked oscillators; voltage-controlled oscillators; CD transport; digital audio; gain peaking reduction; high order phase-locked loop type jitter reduction circuit; maximum phase margin; optimization techniques; sampling; voltage-controlled-crystal-oscillator frequency; Attenuation; Circuit testing; Clocks; Filters; Frequency; Jitter; Phase locked loops; Sampling methods; Signal processing; Signal sampling;
fLanguage
English
Journal_Title
Consumer Electronics, IEEE Transactions on
Publisher
ieee
ISSN
0098-3063
Type
jour
DOI
10.1109/30.485474
Filename
485474
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