Title :
Optimization techniques for high order phase-locked loop type jitter reduction circuit for digital audio
Author_Institution :
Dept. of Electron. Eng., City Univ. of Hong Kong, Hong Kong
fDate :
2/1/1996 12:00:00 AM
Abstract :
Techniques like gain peaking reduction and the selection of voltage-controlled-crystal-oscillator´s (VCXO) frequency are addressed in this paper. The new gain peaking reduction criterion provides far better sampling jitter attenuation when compared with that using maximum phase margin
Keywords :
Hi-Fi equipment; audio equipment; audio-frequency oscillators; circuit optimisation; crystal oscillators; jitter; phase locked loops; phase locked oscillators; voltage-controlled oscillators; CD transport; digital audio; gain peaking reduction; high order phase-locked loop type jitter reduction circuit; maximum phase margin; optimization techniques; sampling; voltage-controlled-crystal-oscillator frequency; Attenuation; Circuit testing; Clocks; Filters; Frequency; Jitter; Phase locked loops; Sampling methods; Signal processing; Signal sampling;
Journal_Title :
Consumer Electronics, IEEE Transactions on
