• DocumentCode
    759676
  • Title

    Optimum architecture for input queuing ATM switches

  • Author

    Majumder, Satya P. ; Gangopadhyay, Ranjan

  • Author_Institution
    Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur, India
  • Volume
    27
  • Issue
    7
  • fYear
    1991
  • fDate
    3/28/1991 12:00:00 AM
  • Firstpage
    555
  • Lastpage
    557
  • Abstract
    An input queueing ATM switch architecture employing the contention resolution called ´scheduling algorithm´ is described. A high efficiency of over 90% can be achieved without any considerable increase in the amount of hardware or contention control speed.
  • Keywords
    queueing theory; switches; time division multiplexing; asynchronous transfer mode; contention control speed; contention resolution; design tradeoff; efficiency; hardware complexity; input queuing ATM switches; scheduling algorithm;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19910350
  • Filename
    100832
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=759676