DocumentCode
759696
Title
An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors
Author
Dunning, Jim ; Garcia, Gerald ; Lundberg, Jim ; Nuckolls, Ed
Author_Institution
Motorola Inc., Austin, TX, USA
Volume
30
Issue
4
fYear
1995
fDate
4/1/1995 12:00:00 AM
Firstpage
412
Lastpage
422
Abstract
A frequency-synthesizing, all-digital phase-locked loop (ADPLL) is fully integrated with a 0.5 μm CMOS microprocessor. The ADPLL has a 50-cycle phase lock, has a gain mechanism independent of process, voltage, and temperature, and is immune to input jitter. A digitally-controlled oscillator (DCO) forms the core of the ADPLL and operates from 50 to 550 MHz, running at 4× the reference clock frequency. The DCO has 16 b of binarily weighted control and achieves LSB resolution under 500 fs
Keywords
CMOS digital integrated circuits; digital phase locked loops; frequency synthesizers; microprocessor chips; voltage-controlled oscillators; 0.5 micron; 50 to 550 MHz; CMOS microprocessor; all-digital PLL; digital phase-locked loop; digitally-controlled oscillator; frequency-synthesizing loop; high-performance microprocessors; Adders; Clocks; Frequency; Jitter; Measurement; Microprocessors; Oscillators; Phase locked loops; Registers; Weight control;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.375961
Filename
375961
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