A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach

Author

Oklobdzija, Vojin G. ; Villeger, David ; Liu, Simon S.

Author_Institution

Integration, Berkeley, CA, USA

Volume

45

Issue

3

fYear

1996

fDate

3/1/1996 12:00:00 AM

Firstpage

294

Lastpage

306

Abstract

This paper presents a method and an algorithm for generation of a parallel multiplier, which is optimized for speed. This method is applicable to any multiplier size and adaptable to any technology for which speed parameters are known. Most importantly, it is easy to incorporate this method in silicon compilation or logic synthesis tools. The parallel multiplier produced by the proposed method outperforms other schemes used for comparison in our experiment. It uses the minimal number of cells in the partial product reduction tree. These findings are tested on design examples simulated in 1 μ CMOS ASIC technology

Keywords

CMOS integrated circuits; VLSI; adders; digital arithmetic; multiplying circuits; 1 μ CMOS ASIC technology; 1 micron; algorithmic approach; fast parallel multipliers; logic synthesis tools; partial product reduction tree; silicon compilation; speed optimized partial product reduction; Application specific integrated circuits; CMOS logic circuits; CMOS technology; Computer graphics; Counting circuits; Log periodic antennas; Optimization methods; Signal processing algorithms; Silicon; Testing;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.485568

Filename

485568