DocumentCode
760026
Title
Pipelined adders
Author
Dadda, Luigi ; Piuri, Vincenzo
Author_Institution
Dept. of Electron. & Inf., Politecnico di Milano, Italy
Volume
45
Issue
3
fYear
1996
fDate
3/1/1996 12:00:00 AM
Firstpage
348
Lastpage
356
Abstract
A well-known scheme for obtaining high throughput adders is a pipeline in which each stage contains an array of half-adders performing a carry-save addition. This paper shows that other schemes can be designed, based on the idea of pipelining a serial-input adder or a ripple-carry adder. Such schemes offer a considerable savings of components while preserving high throughput. These schemes can be generalized by using (p,q) parallel counters to obtain pipelined adders for more than two numbers
Keywords
adders; digital arithmetic; pipeline arithmetic; carry-save addition; half-adders; high throughput adders; parallel counters; pipelined adders; ripple-carry adders; serial-input adder; Adders; Arithmetic; Complexity theory; Computer architecture; Counting circuits; Delay; Image processing; Pipeline processing; Signal processing; Throughput;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.485573
Filename
485573
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