Title :
New algorithm for testing random access memories
Author_Institution :
Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA
fDate :
3/28/1991 12:00:00 AM
Abstract :
A linear time complexity algorithm to test RAMs is presented. The algorithm requires only 7 n read/write operations and provides an extensive fault coverage. The main advantage of the proposed scheme is that a small test time can be achieved.
Keywords :
integrated circuit testing; integrated memory circuits; random-access storage; 7 n read/write operations; RAM chips testing; fault coverage; linear time complexity algorithm; small test time; testing random access memories;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19910362
