Optimal design of life testing for ULSI circuit manufacturing

Author

Pham, Hoang

Author_Institution

EG&G Idaho Inc., Idaho Falls, ID, USA

Volume

5

Issue

1

fYear

1992

fDate

2/1/1992 12:00:00 AM

Firstpage

68

Lastpage

70

Abstract

The life testing of ultra large scale integration (ULSI) circuits is perhaps the most complex manufacturing process found today. This complexity is, in part, the result of product diversity, uncertainty, and changing technologies, and has caused the cost of testing for ULSI circuits to grow exponentially. The author develops a testing cost model and determines the optimum sample size on test which minimizes the expected total system cost assuming that the cost of waiting per unit time and the cost of placing an ULSI circuit on test are given. Numerical examples are also provided to illustrate the methods

Keywords

VLSI; integrated circuit manufacture; integrated circuit testing; life testing; optimisation; ULSI circuit manufacturing; life testing; numerical examples; optimal design; optimum sample size; testing cost model; Circuit testing; Cost function; Integrated circuit manufacture; Integrated circuit technology; Life testing; Manufacturing processes; System testing; Ultra large scale integration; Uncertainty; Very large scale integration;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/66.121982

Filename

121982