Automated State Machine and Timing Characteristic Extraction for RSFQ Circuits

We present a heuristic for the automated extraction of state machine representations of rapid single-flux-quantum (RSFQ) digital logic circuits given a circuit SPICE representation. Furthermore, this heuristic uses the SPICE netlist to extract timing characteristics for the creation of a hardware description language (HDL) implementation of the circuit. This facilitates RSFQ logic design at an HDL level rather than a Josephson junction level. The state machine extraction method can be also used for the automatic creation of test benches for circuit yield analysis, as well as optimization algorithms. An example of the automatic extraction of the state machine representation, timing characterization, and HDL implementation is demonstrated for a complex RSFQ cell.