Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs

Author

Jyh-Ting Lai ; An-Yeu Wu ; Chien-Hsiung Lee

Author_Institution

Graduate Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei

Volume

15

Issue

2

fYear

2007

fDate

2/1/2007 12:00:00 AM

Firstpage

236

Lastpage

240

Abstract

Traditional approaches of automatic gain control (AGC) involve estimating the average power or the peak amplitude over an extended time period, which results in high hardware complexity and a long processing time. Moreover, the accuracy of traditional approaches is seriously degraded by noise and intersymbol interference. In this paper, we propose a joint AGC and equalization (Joint AGC-EQ) scheme, in which the AGC circuitry comprises only one-tenth of the area of a traditional AGC. In addition, the total convergence time of the proposed Joint AGC-EQ is only half that of traditional blind equalization. The scheme is already silicon proven for the application of a Fast Ethernet transceiver using Faraday/UMC 0.18-mum cell libraries

Keywords

VLSI; automatic gain control; transceivers; 0.18 micron; Faraday/UMC cell libraries; VLSI architecture; automatic gain control-equalization algorithm; blind equalization; fast Ethernet transceiver; intersymbol interference; noise; wirelined transceiver designs; Algorithm design and analysis; Amplitude estimation; Circuit noise; Convergence; Degradation; Gain control; Hardware; Intersymbol interference; Transceivers; Very large scale integration; Automatic gain control (AGC); blind equalization; equalizer;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2007.893593

Filename

4142776