• DocumentCode
    762181
  • Title

    Verifying timing consistency in formal specifications

  • Author

    Bartos, Tibor ; Fristacky, Norbert

  • Author_Institution
    Dept. of Comput. Sci., Slovak Tech. Univ., Bratislava, Slovakia
  • Volume
    13
  • Issue
    1
  • fYear
    1996
  • Firstpage
    8
  • Lastpage
    15
  • Abstract
    The authors´ algorithm formally verifies the rule set that expresses timing discipline in digital system specifications. Their algorithm is based on a higher level behavioral specification model and concerns formal consistency verification at the design level of the system specification development procedure
  • Keywords
    formal specification; formal verification; hardware description languages; logic CAD; timing; VHDL; algorithm; design; digital system specifications; formal consistency verification; formal specifications; higher level behavioral specification; rule set; timing; timing consistency verification; Circuit synthesis; Formal specifications; Formal verification; Hydrogen; Logic functions; Testing; Time factors; Timing;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.485778
  • Filename
    485778
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=762181