• DocumentCode
    762196
  • Title

    Net scheduling in high-level synthesis

  • Author

    Prihozhy, Anatoly

  • Author_Institution
    Dept. of Comput. Syst., State Univ. of Inf. & Radioelectron., Minsk, Byelorussia
  • Volume
    13
  • Issue
    1
  • fYear
    1996
  • Firstpage
    26
  • Lastpage
    35
  • Abstract
    A new net scheduling and allocation model generates net schedules that minimize either execution time or resources. The author tested the model within a VHDL-based high-level synthesis system called Ahiles
  • Keywords
    high level synthesis; logic design; scheduling; Ahiles; allocation model; execution time; high-level synthesis; net scheduling; Circuit synthesis; Control system synthesis; Digital circuits; Hardware; High level synthesis; Multiplexing; Partitioning algorithms; Processor scheduling; Scheduling algorithm; Signal synthesis;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.485780
  • Filename
    485780
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=762196