A 2.4 GHz ULP Reconfigurable Asymmetric Transceiver for Single-Chip Wireless Neural Recording IC

This paper presents a 2.4 GHz ultra-low-power (ULP) reconfigurable asymmetric transceiver and demonstrates its application in wireless neural recording. Fabricated in 0.13 μm CMOS technology, the transceiver is optimized for sensor-gateway communications within a star-shaped network, and supports both the sensor and gateway operation modes. Binary phase-shift keying (BPSK) modulation with high data rate (DR) of 1 to 8 Mbps is used in the uplink from sensor to gateway, while on-off keying (OOK) modulation with low DR of 100 kbps is adopted in the downlink. A fully integrated Class-E PA with moderate output power has also been proposed and achieves power efficiency of 53%. To minimize area usage, inductor reuse is adopted between PA and LNA, and eliminates the need of lossy T/R switch in the RF signal path. When used as sensor, the transceiver with frequency locked phase-locked loop (PLL) achieves TX (BPSK) power efficiency of 28% @ 0 dBm output power, and RX (OOK) sensitivity of -80 dBm @ 100 kbps while consuming only 780 μW. When configured as gateway, the transceiver achieves sensitivity levels of -92, -84.5, and -77 dBm for 1, 5, and 8 Mbps BPSK, respectively. The transceiver is integrated with an 8-channel neural recording front-end, and neural signals from a rat are captured to verify the system functionality.