Title :
High-speed parallel CRC circuits in VLSI
Author :
Pei, Tong-Bi ; Zukowski, Charles
Author_Institution :
Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
fDate :
4/1/1992 12:00:00 AM
Abstract :
The use of VLSI technology to speed up cyclic redundancy checking (CRC) circuits used for error detection in telecommunications systems is investigated. By generalizing the analysis of a parallel prototype, performance is estimated over a wide range of external constraints and design choices. It is shown that parallel architectures fall somewhat short of ideal speedups in practice, but they should still enable current CMOS technologies to go well beyond 1 Gb/s data rates
Keywords :
VLSI; error detection; parallel architectures; telecommunication equipment; CMOS technologies; VLSI; cyclic redundancy checking; error detection; high speed parallel CRC circuits; parallel architectures; telecommunications systems; Arithmetic; CMOS technology; Circuits; Clocks; Cyclic redundancy check; Data communication; Optical feedback; Polynomials; Prototypes; Very large scale integration;
Journal_Title :
Communications, IEEE Transactions on
