Real-time simulation of videophone image coding algorithms on reconfigurable multicomputers

The simulation at bit stream level of motion video image coding algorithms provides an effective means of algorithm development and evaluation. The paper describes the problems encountered in using a large reconfigurable transputer-based multicomputer to simulate, in real-time, realistically complex videophone image coding algorithms. A primary aim was to enable the output of all stages of the algorithm to be displayed graphically. This led to further communications bandwidth requirements which demanded that unusual processor network topologies were experimented with. For the large numbers of transputers used, it was found that irregular topologies provide better performance than previously popular regular ones.