• DocumentCode
    765664
  • Title

    Gate resistance modeling of multifin MOS devices

  • Author

    Wu, Wen ; Chan, Mansun

  • Author_Institution
    Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China
  • Volume
    27
  • Issue
    1
  • fYear
    2006
  • Firstpage
    68
  • Lastpage
    70
  • Abstract
    This letter studies the effects of geometrical parameters (fin spacing, fin height and polysilicon thickness) on the gate resistance of multifin MOS devices. An effective lumped resistance model derived from distributed RC network is formulated and verified using a two-dimensional simulator. Based on the model, a design guideline for the fin spacing to minimize the gate resistance and RC delay is provided to design multifin MOS devices for high frequency applications.
  • Keywords
    MOSFET; RC circuits; semiconductor device models; FinFET device; RC delay; distributed RC network; gate resistance modeling; lumped resistance model; multifin MOS devices; Councils; Delay; Equations; FinFETs; Geometry; Guidelines; MOS devices; Radio frequency; Semiconductor device modeling; Solid modeling; FinFET; gate resistance; radio frequency (RF);
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/LED.2005.861599
  • Filename
    1561458
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=765664