Heat Dissipation in Nanocomputing: Lower Bounds From Physical Information Theory

Computing circuits that irreversibly discard information unavoidably dissipate heat. Dissipative costs resulting from information loss, while insignificant in CMOS technology, may be dominant or even prohibitive in some dense, high-speed post-CMOS nanocomputing circuits that employ logically irreversible operations. In transistor-based paradigms, dissipation costs associated with logical irreversibility may be supplemented by additional unavoidable costs associated with particle supply required to maintain the computational “working substance.” These considerations motivate determination of fundamental lower bounds on the dissipative cost of computation that can be applied to concrete nanocomputing technology proposals. In this paper, we present a methodology for the determination of such bounds and illustrate its application to half-adder circuits implemented in the quantum cellular automata and nano-wire-based nano-application specific-integrated circuit paradigms. The resulting bounds reflect fundamental costs inherent in the underlying computational strategies employed by these circuits. Prospective use of this methodology as an assessment tool for post-CMOS nanocomputing technology proposals is discussed.