Column-level passive sample and column-shared active readout structure for high speed, low power ROIC

Author

Wang Guannan ; Lu Wengao ; Liu Dahe ; Zhang Yacong ; Chen Zhongjian

Author_Institution

Nat. Key Lab. of Sci. & Technol. on Micro/Nano Fabrication, Peking Univ., Beijing, China

Volume

51

Issue

5

fYear

2015

fDate

3 5 2015

Firstpage

390

Lastpage

392

Abstract

A novel odd-even column-level passive sample and column-shared active readout structure is proposed to realise a high speed, low power and low noise readout integrated circuit (ROIC). This structure reduces the number of operational amplifiers (OPAs) in each column and decreases the power consumption of the column capacitive transimpedance amplifier (CTIA) and output buffer. Compared to the traditional design for medium-scale array ROIC, power consumption of a single column is reduced by 80%. A 320 × 320 array ROIC has been designed for indium antimonide (InSb) cooled infrared detector using the novel structure. The chip is fabricated in the 0.35 μm CMOS process. The total power consumption is <;55 mW when operating at 200 Hz frame rate with four outputs and the linearity is 99.95%.

Keywords

CMOS integrated circuits; indium compounds; infrared detectors; integrated circuit design; low-power electronics; operational amplifiers; readout electronics; CMOS process; CTIA; InSb; column capacitive transimpedance amplifier; column-level passive sample structure; column-shared active readout structure; cooled infrared detector; high speed low noise readout IC; low power ROIC; medium-scale array design; power consumption; size 0.35 mum;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el.2014.3342

Filename

7047393