Programmable low-noise fast-settling fractional-N CMOS PLL with two control words for versatile applications

Frequency synthesisers are essential parts of various communication systems. The development of application versatile CMOS fractional-N synthesisers has been demanding. In the paper, a novel scheme for programmable fractional-N phase-locked loop based synthesisers is proposed. Two control words are used for achieving the programmability features. The relationships of step size and output frequency with reference frequency, input data and modulus division factors are described. A 2.4 GHz CMOS 12-bit /spl Sigma//spl Delta/ fractional-N synthesiser has been implemented using 0.35 /spl mu/m CMOS Chartered Semiconductor Manufacturing (CSM) process. Using the two input data words, its programmable features have been demonstrated. It has a phase noise of -110 dBc/Hz at 1 MHz offset and a settling time of less than 37 /spl mu/s. It consumed 11 mA current while operated from a 3 V supply. Synthesiser operation and measurement results are provided.