Title :
Low-latency, high-speed numerically controlled oscillator using progression-of-states technique
Author :
Thompson, Matthew
Author_Institution :
Interstate Electron. Corp., Anaheim, CA, USA
fDate :
1/1/1992 12:00:00 AM
Abstract :
A progression-of-states design technique for numerically controlled oscillators (NCOs) has measured a decrease in 16-bit accumulator latency to two clock cycles for a 130-MHz device in a 1.0-μm CMOS gate array. An enhanced version derived and simulated directly from fabricated device has been projected to accumulate at 267 MHz
Keywords :
CMOS integrated circuits; digital integrated circuits; frequency synthesizers; oscillators; 1 micron; 130 MHz; 16 bit; 267 MHz; CMOS; NCO; accumulator latency; frequency synthesis; gate array; high speed oscillator; low latency; numerically controlled oscillators; progression-of-states design technique; two clock cycle latency; Application specific integrated circuits; Clocks; Costs; Delay; Equations; Frequency conversion; Frequency synthesizers; Oscillators; Phase locked loops; Tuning;
Journal_Title :
Solid-State Circuits, IEEE Journal of
