Optimum tapered buffer

Author

Prunty, Craig ; Gal, Laszlo

Author_Institution

UNISYS Corp., San Diego, CA, USA

Volume

27

Issue

1

fYear

1992

fDate

1/1/1992 12:00:00 AM

Firstpage

118

Lastpage

119

Abstract

Driver stages in MOS circuitry have been extensively investigated during the last decade. recently a tapering rule for CMOS buffers was derived showing that the tapering factor (β) is determined by the ratio of output to input capacitance. The derivation fails to account for the correlation between the short-circuit current and β. As a result, the derived formula consistently overpredicts the value of optimum β, especially for large input/output capacitance ratios. The authors present a modified formula and a method to account for the effect of the short-circuit current that is viable for buffer stages over a wide range of output/input capacitance ratios; this newly derived formula accurately predicts the optimum tapering factors for BiCMOS as well as CMOS buffer chains

Keywords

BIMOS integrated circuits; CMOS integrated circuits; amplifiers; buffer circuits; driver circuits; BiCMOS buffers; CMOS buffers; buffer chains; driver stages; input/output capacitance ratios; modified formula; optimum tapered buffer; optimum tapering factors; short-circuit current; tapering rule; Analytical models; BiCMOS integrated circuits; Capacitance; Capacitors; Delay; Driver circuits; Helium; Predictive models; Semiconductor device modeling; Termination of employment; Threshold voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.109565

Filename

109565