Latch-up on CMOS/EPI devices

Author

Chapuis, T. ; Erems, H. Constans ; Rosier, L.H.

Author_Institution

Centre Nat. d´´Etudes Spatiales, Toulouse, France

Volume

37

Issue

6

fYear

1990

fDate

12/1/1990 12:00:00 AM

Firstpage

1839

Lastpage

1842

Abstract

A dedicated latch-up test system has been developed and was used on two beam lines, the GANIL cyclotron and the IPN Tandem Van de Graaff located in Caen and Orsay (France). The main characteristics of these facilities are presented. Several VLSI circuits were irradiated, and the latchup phenomenon was detected on eight CMOS/EPI devices, revealing various ranges of sensitivity. Recording of the value and rising edge of latchup current was also performed. The problem of whether or not latchup-sensitive circuits should be used for space projects and the need for studies of component design hardening, system design hardening, and latchup rate prediction are addressed. Data are presented on several CMOS/EPI devices demonstrating that an epitaxial layer cannot efficiently achieve latchup immunity for some of the latest technologies

Keywords

CMOS integrated circuits; VLSI; integrated circuit testing; ion beam effects; radiation hardening (electronics); test facilities; CMOS/EPI devices; GANIL cyclotron; IPN Tandem Van de Graaf; VLSI circuits; component design hardening; epitaxial layer; ion beam irradiation; latch-up test system; latchup current; latchup immunity; sensitivity; system design hardening; Automatic control; CMOS technology; Circuit testing; Control systems; Current supplies; Cyclotrons; Ion accelerators; Space technology; System testing; Very large scale integration;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.101198

Filename

101198