A novel systematic approach for equivalent model extraction of embedded high-speed interconnects in time domain

Based on time-domain scattered data, an efficient systematic approach in the time domain has been proposed to extract the SPICE-compatible models of embedded high-speed interconnects. The approach combines the layer-peeling technique and the generalized pencil-of-matrix method to obtain a pole-residue representation of the step response of the interconnects. An order-reduction procedure is implemented based on the bandwidth criterion to find the optimum pole-residue representation of the interconnects with minimum pole numbers. The SPICE-compatible lumped circuits are then systematically extracted from the pole-residue rational functions. The discontinuous microstrip lines and bonding wire structure are used to demonstrate the validity of the proposed approach. Good agreement is seen between the modeled and measured transient response. The advantages of this approach are the de-embedding ability for arbitrary nonuniform interconnects, systematically obtaining lower order and more accurate SPICE-compatible circuits, and broad-band performance of the extracted circuits.