• DocumentCode
    769246
  • Title

    Line Equalizer for a Digital Subscriber Loop Employing Switched Capacitor Technology

  • Author

    Suzuki, Toshiro ; Takatori, Hiroshi ; Ogawa, Makoto ; Tomooka, Keiji

  • Author_Institution
    Central Research Laboratory, Hitachi Ltd., Kokubunji, Tokyo, Japan
  • Volume
    30
  • Issue
    9
  • fYear
    1982
  • fDate
    9/1/1982 12:00:00 AM
  • Firstpage
    2074
  • Lastpage
    2082
  • Abstract
    A new line equalizer system for time compression burstmode digital suhscriber loop transmission that can equalize a line with multiple bridged taps (BT\´s) is developed. Using the developed equalizer, up to 5 km (0.4 mmφ) line length and four BT connections can be equalized at a data rate of 80 kbits/s in each direction. The equalizer is composed of a variable gain \\surd {f} step equilizer, a decision feedback automatic equalizer, and a newly developed wave difference method (WDM) timing extraction PLL. In order to fabricate the whole circuit on a single-chip LSI, most of the analog portion is organized using; switched capacitor technology. In this paper, the system design concept, circuit configuration, and results of simulations and experiiments are described.
  • Keywords
    Echo control; Equalizers; Subscriber networks; Switched-capacitor filters; Capacitors; Circuits; DSL; Data mining; Equalizers; Feedback; Gain; Phase locked loops; Timing; Wavelength division multiplexing;
  • fLanguage
    English
  • Journal_Title
    Communications, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0090-6778
  • Type

    jour

  • DOI
    10.1109/TCOM.1982.1095697
  • Filename
    1095697