Radiations hardening of a high voltage IC technology (BCDMOS)

Author

Desko, John C., Jr. ; Darwish, Mohamed N. ; Dolly, Martin C. ; Goodwin, Charles A. ; Dawes, William R., Jr. ; Titus, Jeffrey L.

Author_Institution

AT&T Bell Lab., Reading, PA, USA

Volume

37

Issue

6

fYear

1990

fDate

12/1/1990 12:00:00 AM

Firstpage

2083

Lastpage

2088

Abstract

A program was undertaken to radiation harden AT&T´s existing power integrated circuit technology (BCDMOS). The BCDMOS technology is described. The radiation hardening approach is outlined. The modifications made to standard technology in an effort to harden the CMOS, DMOS, and NPN devices to four radiation environments (total dose, dose rate, single event upset (SEU), and neutrons) are discussed. Steps taken improve the performance of these devices to meet the circuit requirements are described. The tradeoffs involving the different devices and the different radiation environments are discussed. Initial results indicate a substantial improvement in hardness over existing commercial technology

Keywords

BIMOS integrated circuits; integrated circuit technology; neutron effects; power integrated circuits; radiation hardening (electronics); BCDMOS technology; CMOS hardening; DMOS hardening; NPN transistor hardening; SEU; dose rate; gamma dot; high voltage IC technology; modifications to standard technology; power integrated circuit technology; radiation environments; radiation hardening; single event upset; total dose; tradeoffs; Breakdown voltage; CMOS process; CMOS technology; Circuits; DC-DC power converters; Diodes; Fabrication; Radiation hardening; Resistors; Temperature;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.101234

Filename

101234