Low-cost logarithmic CMOS image sensing by nonlinear analog-to-digital conversion

In this paper we present a CMOS image sensor design with a better sensitivity to low light intensity. This feature is achieved through a multi-resolution analog-to-digital converter (ADC). By doing so, the photo-electrical characteristic of a sensor cell can is finely tuned. A cost-effective architecture for realizing the required ADC is also proposed. This architecture leads to a faster conversion time as well as a smaller area. A simulation environment with post-layout accuracy is incorporated to demonstrate the advantages. It shows that a number of images can be captured more clearly than a traditional sensor.