• DocumentCode
    77011
  • Title

    Effect of {\\rm O}_{2} Flow Rate During Channel Layer Deposition on Negative Gate Bias Stress-Induced V_{\\r</h1></div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Author</span></div><div class='col-12 col-md-9 leftDirection leftAlign'><h2 class='mb-0 fw-semibold'>Xiang Xiao ; Wei Deng ; Shipeng Chi ; Yang Shao ; Xin He ; Longyan Wang ; Shengdong Zhang</h2></div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Author_Institution</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>Sch. of Electron. & Comput. Eng., Peking Univ., Shenzhen, China</div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Volume</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>60</div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Issue</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>12</div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>fYear</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>2013</div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>fDate</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>Dec. 2013</div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Firstpage</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>4159</div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Lastpage</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>4164</div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Abstract</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>The effect of O<sub>2</sub> flow rate during the sputtered deposition of channel layer on the negative gate-bias stress (NGBS)-induced threshold voltage (V<sub>th</sub>) instability of a-IGZO TFTs is investigated. It is shown that the negative gate-bias stress results in a negative V<sub>th</sub> shift of the a-IGZO TFTs, and the shift amount decreases with the increase in O<sub>2</sub> flow rate. It is proposed that the V<sub>th</sub> shift originates from the electron-detrapping from the oxygen vacancy-related donor-like states at the channel/dielectric interface. As the O<sub>2</sub> flow rate increases, the density of donor-like states is decreased and the distribution of neutral donor-like states below E<sub>F</sub> is also reduced. Therefore, the amount of Vth shift caused by the positively charged trap states and electrons injecting into the channel from the donor-like states decreases with the O<sub>2</sub> flow rate increase. It is also shown experimentally that while the electrical characteristics of the a-IGZO TFTs are generally improved with the O<sub>2</sub> flow rate increase, they are degraded if an excess O<sub>2</sub> is introduced. An optimal O<sub>2</sub>/Ar flow rate ratio of about 5 sccm/45 sccm is suggested to make a trade-off between the electrical performances and the gate-bias stress-induced V<sub>th</sub> instability.</div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Keywords</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>negative bias temperature instability; thin film transistors; NGBS-induced threshold voltage; a-IGZO TFT; channel layer deposition; channel/dielectric interface; charged trap states; electron detrapping; flow rate; gate bias stress induced instability; negative gate bias stress; neutral donor like states; vacancy related donor-like states; Educational institutions; Logic gates; Sputtering; Stress; Thin film transistors; Threshold voltage; <formula formulatype=${rm O}_{2}$ flow rate; Amorphous indium-gallium-zinc-oxide (a-IGZO); donor-like states; instability; thin film transistors (TFTs);

  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2013.2286636
  • Filename
    6651789
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=77011