An F8 Microprocessor-Based Breadboard for the Simulation of Communication Links Using Rate 1/2 Convolutional Codes and Viterbi Decoding

This paper presents an F8 microprocessor-based breadboard for the simulation of communication links using rate ½ binary convolutional codes in connection with Viterbi decoding, and which can be of value in the collection and analysis of statistical data relevant to such systems. The main purpose in the implementation of such a scheme has been to alleviate the high cost of running such simulations on macro or mini digital computers. Another advantage resides in the fact that the low cost of implementation of the final system makes it attractive as a teaching and training tool for young engineers in this important new field of communication theory. Moreover, with slight modifications, the system can be extended in a straightforward manner to handle a more general class of convolutional codes than the rate ½ codes, as well as transmission channels with more complex error statistics than the simple and rather academic binary symmetrical channel.