Series resistance calculation for source/drain extension regions using 2-D device simulation

Series resistance in the source/drain region is becoming a bottleneck for MOS device performance. A rigorous, simulation-based method for calculating resistance components that correctly accounts for current spreading is presented. Resistance calculation strategies used to project lateral abruptness requirements for future scaling, based on partitioning the device into vertical strips, are shown to cause substantial errors when current spreading occurs. This can result in an overestimate of the benefits of abrupt junctions. The physical resistances obtained from simulated devices are compared with the extracted resistances from the shift-and-ratio method. Discrepancies can be explained based on violation of the basic assumptions of the shift-and-ratio method: that series resistance is bias independent and the channel resistance is directly proportional to the channel length. A new extraction method that relaxes these assumptions is presented and used to provide deeper understanding in the application of the shift-and-ratio method to deep submicron devices