DocumentCode :
772365
Title :
Optimizing Address Assignment and Scheduling for DSPs With Multiple Functional Units
Author :
Xue, Chun ; Shao, Zili ; Zhuge, Qingfeng ; Xiao, Bin ; Liu, Meilin ; Sha, Edwin H M
Author_Institution :
Dept. of Comput. Sci., Texas Univ., Richardson, TX
Volume :
53
Issue :
9
fYear :
2006
Firstpage :
976
Lastpage :
980
Abstract :
Digital signal processors provide dedicated address generation units (AGUs) that are capable of performing address arithmetic in parallel to the main data path. Address assignment, optimization of memory layout of program variables to reduce address arithmetic instructions by taking advantage of the capabilities of AGUs, has been studied extensively for single-functional-unit (FU) processors. In this brief, we exploit address assignment and scheduling for multiple-FU processors. We propose an efficient address assignment and scheduling algorithm for multiple-FU processors. Experimental results show that our algorithm can greatly reduce schedule length and address operations on multiple-FU processors compared with the previous work
Keywords :
digital signal processing chips; parallel architectures; processor scheduling; address arithmetic; address assignment; address generation unit; digital signal processor; multiple functional unit processors; Arithmetic; Digital signal processing; Digital signal processors; Processor scheduling; Registers; Scheduling algorithm; Signal generators; Signal processing; Signal processing algorithms; VLIW; Address assignment; address generation unit (AGU); digital signal processor (DSP); multiple functional units (FUs); scheduling;
fLanguage :
English
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-7747
Type :
jour
DOI :
10.1109/TCSII.2006.880026
Filename :
1705078
Link To Document :
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