Static timing analysis for level-clocked circuits in the presence of crosstalk

Static timing analysis is instrumental in efficiently verifying a design´s temporal behavior to ensure correct functionality at the required frequency. This paper addresses static timing analysis in the presence of crosstalk for circuits containing level-sensitive latches, typical in high-performance designs. The paper focuses on two problems. First, coupling in a sequential circuit can occur because of the proximity of a victim´s switching input to any periodic occurrence of the aggressor´s input switching window. This paper shows that only three consecutive periodic occurrences of the aggressor´s input switching window must be considered. Second, an arrival time in a sequential circuit is typically computed relative to a specific clock phase. The paper proposes a new phase shift operator to align the aggressor´s three relevant switching windows with the victim´s input signals. This paper solves the static analysis problem for level-clocked circuits iteratively in polynomial time, and it shows an upper bound on the number of iterations equal to the number of capacitors in the circuit. The contributions of this paper hold for any discrete overlapping coupling model. The experimental results demonstrate that eliminating false coupling allows finding a smaller clock period at which a circuit will run.